About this role
Role Overview
- Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
- Be exposed and work on a variety of challenging designs (including high cell count and HS blocks).
- Resolving complex timing and congestion problems.
- Daily work involves all aspects of physical design chip development (RTL2GDS)
- synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
- Taking part in flows development.
Requirements
- B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent experience.
- Proven experience in RTL2GDS flows and methodologies (advantage)
- Knowledge in physical design flows and methodologies (PNR, STA, physical verification). (advantage)
- Understanding of all aspects of Physical construction and Integration.
- Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
- Great teammate, enthusiastic in solving complex problem together with peers.