Digital Integrated Circuit Design Verification Engineer

Snap Inc. is a technology company focused on enhancing communication through innovative products like Snapchat and AR glasses. They are seeking a Design Verification Engineer to work on display Integrated Circuits for AR, collaborating with various engineering teams to develop and implement verification test plans and methodologies.

Responsibilities:

• Work as part of a multi-disciplinary team designing display Integrated Circuits for AR
• Work closely with digital design, analog logic, software and verification engineers
• Develop and implement UVM-based and assertion-based testbenches
• Create and execute verification test plans, including functional coverage and code coverage
• Utilize Siemens Questa tool set for verification and debug tasks
• Specify and configure tools and create automation

Requirements:

• Strong knowledge of UVM and SystemVerilog for advanced verification methodologies
• Strong knowledge of digital functional simulation, and tools such as Siemens Questa
• Strong knowledge of good Verilog RTL coding practices
• Scripting and automation, such as TCL, Make, Perl, Python and Shell scripts in Linux environment
• Excellent written and verbal English communication
• BSEE or MSEE or relevant years of experience
• 10 + years of experience in ASIC Design Verification
• Experience with entire verification process from planning to sign-off
• Experience with Siemens' UVM Framework
• Experience in emulation
• Experience in RTL design
• Familiarity with video and display systems, MIPI, AMBA, I2C, SPI protocols and embedded microcontroller
• Familiarity with ASIC test or production flow
• Ideal candidate is a self-starter, can organize complex issues and drive them to closure
• Able to multitask and prioritize