Encore Semi, Inc. is a company specializing in ASIC synthesis, seeking a Senior ASIC Synthesis Engineer. The role involves leading RTL-to-gates implementation, driving synthesis strategy, and mentoring junior engineers while collaborating with cross-functional teams to optimize design processes.
Responsibilities:
- Lead RTL-to-gates implementation using Cadence Genus for GF 22FDX
- Drive synthesis strategy, constraint management, and multi-mode multi-corner (MMMC) optimization
- Act as a technical mentor for junior engineers, ensuring high-quality netlists with robust DFT integration
- Collaborates cross-functionally with RTL, verification, and backend teams to minimize ECO cycles and accelerate signoff readiness
Requirements:
- 8+ years' hands-on experience in ASIC synthesis with Cadence or Synopsys tools
- Deep expertise in SDC constraint writing, clock gating, and hierarchical synthesis
- Familiarity with GF 22FDX standard cells, libraries, and foundry requirements
- Proven track record of leading synthesis flow improvements and methodology development