Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. They are seeking a highly skilled Physical Design Engineer to drive the critical Die-to-Die Physical Implementation from RTL to GDSII, focusing on high-speed interfaces for multi-die architectures.

Responsibilities:

• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout
• Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off
• Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS
• Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure
• Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug)
• Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification

Requirements:

• A seasoned ASIC Physical Design Engineer with 5+ years at advanced nodes (7nm or below) and multiple successful tapeouts
• Strong in full-chip implementation, comfortable owning blocks from RTL to GDSII across synthesis, floorplanning, place-and-route, CTS, and sign-off
• Deeply familiar with high-speed interfaces (D2D, PCIe, HBM, SerDes) and the physical challenges that come with them (timing, signal integrity, power integrity)
• Detail-oriented and methodical with STA, constraints, and closure for complex, high-speed designs
• A hands-on problem solver who enjoys collaborating across analog, digital, and full-chip teams to debug tough issues
• Lead Die-to-Die (D2D) physical implementation and closure, taking high-speed D2D PHYs/controllers from netlist to tapeout
• Own the full PD flow (RTL-to-GDSII): synthesis, floorplanning, P&R, CTS, optimization, and sign-off
• Drive timing and verification, including full STA (setup/hold), SI analysis (crosstalk, IR drop), and achieving sign-off quality DRC/LVS
• Improve and maintain physical design methodologies, flows, and automation scripts (Tcl, Python), with specific focus on D2D routing, power grid design, and timing closure
• Partner closely with full-chip/chiplet teams to meet all tapeout requirements and with the analog design team to resolve interface issues (LEF/LIB, constraints, integration/debug)
• Apply strong EDA tool expertise across Synopsys/Cadence/Mentor for implementation, analysis, and verification
• Bring a solid academic foundation: B.S./M.S. in EE/CE or related field