Key skills
RTL design experienceVerilog / SystemVerilogUAlink protocolhigh-speed interconnectsmicro-architecture understandingsynthesis toolsdebugging skillsSoC integrationlow-power design knowledgeCDC/RDC analysis tools
About this role
Element Technologies is seeking an experienced RTL Design Engineer with a strong background in UAlink-based high-speed interconnect design. The role involves micro-architecture development, RTL coding, and integration of complex protocol-driven blocks.
Responsibilities:
- Micro-architecture development
- RTL coding
- Integration of complex protocol-driven blocks
Requirements:
- 5+ years of RTL design experience
- Strong Verilog / SystemVerilog coding skills
- Hands-on experience designing and implementing UAlink protocol
- Experience with high-speed interconnects (PCIe, CXL, or similar)
- Strong understanding of micro-architecture, FSM design, and timing closure
- Experience with synthesis tools (DC/Genus or equivalent)
- Good debugging skills and experience working closely with DV teams
- SoC integration experience
- Low-power design knowledge
- Experience with CDC/RDC analysis tools