Lead Digital ASIC Design Engineer

K2 Space Corporation is building the largest and highest-power satellites ever flown, aiming to unlock unprecedented performance levels in space technology. They are seeking a Lead Digital ASIC Design Engineer to drive the design and implementation of digital subsystems for advanced wireless SoCs while managing a team of engineers and contributing to cutting-edge communication systems for space applications.

Responsibilities:

• Lead and manage a team of digital design engineers, providing technical mentorship, career development, and performance management
• Manage development schedules, track deliverables, and report status to senior leadership and cross-functional teams
• Contribute to design and implementation of microarchitecture and RTL for key digital blocks in wireless SoCs, including DSP systems, interfaces, and control logic
• Collaborate with system architects to translate high-level DSP algorithms and chip specifications into efficient hardware implementations
• Develop RTL for complex digital subsystems such as filters, beamformers, FFT/IFFT engines, and digital front-ends
• Contribute to design and integration of digital blocks for interfaces, power management, clocking, reset, test, and debug infrastructure
• Work with analog/mixed-signal teams to define and implement digital-analog interfaces, calibration engines, and control logic
• Optimize designs for power, performance, and area (PPA) while meeting timing, area, and power constraints
• Collaborate with synthesis and backend teams to achieve timing closure and resolve design issues
• Contribute to verification planning and work closely with verification teams to validate complex digital subsystems
• Participate in chip bring-up and lab validation activities for digital subsystems
• Support products through production and spaceflight operations
• Mentor junior engineers and contribute to team technical growth and best practices

Requirements:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks or subsystems
• 3+ years of experience leading ASIC design teams or projects, including mentoring engineers and managing deliverables
• Strong proficiency in RTL design using SystemVerilog or Verilog, with experience in synthesis and linting tools
• Experience in microarchitecture definition and implementation based on architectural guidelines and analysis
• Hands-on experience with timing closure, working effectively with synthesis and static timing analysis teams
• Familiarity with DFT concepts and tools for scan and BIST insertion
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and verification methodologies
• Experience with DSP blocks for wireless communication systems (e.g., OFDM, MIMO, channel estimation, DFE)
• Proficiency with industry-standard EDA tools for design, synthesis, static timing analysis, and power analysis (e.g., Synopsys, Cadence, Siemens tools)
• Strong debugging, problem-solving, and communication skills with ability to work effectively in cross-functional teams
• Experience in wireless SoC development (e.g., cellular, Wi-Fi, satellite, or mmWave systems) with successful tapeouts
• Design experience with datapath architectures, flow control, arbitration, FIFO, DMA, IOMMU, and SoC bus architectures
• Experience with ARM's AXI/AHB bus architectures and protocols, and serial interfaces such as SPI, I3C, UART
• Familiarity with DSP algorithm modeling using MATLAB, Python, or C++ and converting models into RTL implementations
• Experience working with FEC, baseband PHYs, or digital beamforming architectures
• Knowledge of digital calibration and control of RF/mixed-signal front ends
• Exposure to hardware-software co-design and embedded processor integration
• Experience working in fast-paced startup or cross-functional, geographically distributed teams