Senior Digital ASIC Design Engineer

K2 Space Corporation is building the largest and highest-power satellites ever flown, and they are seeking a highly skilled Senior Digital ASIC Design Engineer to lead the design and implementation of digital subsystems for advanced wireless SoCs. The role involves architecting, developing, and implementing new SoC sub-systems for satellite communications, contributing to the design of state-of-the-art mixed-signal SoCs.

Responsibilities:

• Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog or Verilog
• Translate algorithmic and architectural specifications into synthesizable RTL
• Implement DSP functions such as filtering, FFT/IFFT, or beamforming
• Convert chip specifications into RTL using internal IPs and external IPs
• Design and develop RTL for interfaces, power management, clocking, reset, test & debug
• Partner with analog/mixed-signal teams to define digital-analog interfaces, calibration engines, and control logic
• Optimize designs for power, performance, and area (PPA) and support timing closure through synthesis and backend collaboration
• Contribute to block-level integration, synthesis, and timing closure
• Participate in design reviews, functional verification, and timing closure
• Participate in chip bring-up and lab validation of complex digital subsystems
• Support your product through production and spaceflight

Requirements:

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
• 5+ years of hands-on experience in digital ASIC design
• Proficiency in RTL design (SystemVerilog or Verilog), synthesis, and linting tools
• Experience in micro-architecture definition from architecture guideline and model analysis
• Experience with DFT tools for scan and BIST insertion
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and formal verification
• Familiarity with EDA tools for design, simulation, linting, and STA
• Experience implementing DSP functions in hardware
• Understanding of digital design best practices including clock domain crossing (CDC), power domain management, and design-for-test (DFT)
• Strong debugging, problem-solving, and communication skills
• Prior experience in wireless SoC development (e.g. cellular, Wi-Fi, satellite, or mmWave systems) and successful tapeouts in advanced design nodes
• Design experience in datapath, flow control, arbitration, FIFO, DMA, IOMMU, SoC bus architecture, ARM's AXI/AHB bus architecture & protocols, serial interfaces such as SPI, I3C, UART
• Familiarity with DSP algorithm modeling (MATLAB, Python, or C++) and converting models into RTL
• Hands-on experience with lag bring-up and post-silicon debug
• Knowledge of digital calibration and control of RF/mixed-signal front ends
• Exposure to hardware-software co-design and embedded process integration
• Experience working in cross-functional, geographically distributed teams