Physical  Design Engineer- Work From Home !

Alpha Consulting Corp. is seeking a Physical Design Engineer to advance cutting-edge quantum chip technologies. The role involves executing digital physical design flows, integrating complex digital blocks, and collaborating with cross-functional teams to ensure high-quality designs meet aggressive timelines.

Responsibilities:

• End-to-End Physical Design Execution: Own and execute the digital physical design flow from RTL to GDSII using both the Cadence and Synopsys tool suites, including Cadence Innovus (place and route), and Cadence Tempus (timing analysis and closure), and Synopsys Design Compiler (synthesis)
• Design Integration: Integrate and manage complex digital blocks and subsystems, ensuring seamless interaction with analog and quantum components. Key tasks include floorplanning, power planning, and other integration activities
• Physical Verification and Signoff: Guide designs through physical checking and verification processes, including DRC, LVS, and other signoff criteria, to ensure manufacturability and compliance with foundry requirements
• Tapeout Delivery: Drive designs to successful RIT (Release to Tapeout), ensuring all physical and timing signoff requirements are met
• Collaboration and Communication: Work closely with circuit designers, researchers, and tool developers to resolve design challenges, optimize flows, and ensure alignment across disciplines. Mentor junior colleagues to develop skills in PD tools and methodologies
• Problem Solving and Debug: Apply strong analytical and debugging skills to identify and resolve design and flow issues, with a focus on quality and efficiency
• Continuous Improvement: Contribute to the development and refinement of physical design methodologies, leveraging scripting and automation to enhance productivity and design quality
• Innovation Support: Engage with emerging technologies and methodologies, including those relevant to quantum computing, to help shape the future of chip design

Requirements:

• BS Computer/Electrical Engineering or related
• 5+ years of experience with industry-standard Physical Design tools such as the Cadence tool suite, including Innovus, & Tempus (e.g. timing closure), and Synopsys Design Compiler
• Knowledge of physical checking and verification (e.g. DRC/LVS)
• Proficiency in Linux command-line and scripting languages (Python, Tcl)
• Excellent trouble-shooting skills for environment setup, license issues, tool invocation errors, and missing dependencies
• Ability to read and follow internal documentation, interpret errors, and self-debug common onboarding issues
• Demonstrated ability to onboard quickly into a complex internal or proprietary tool environment
• Demonstrated ability to deliver high-quality deliverables with a strong attention to detail
• Ability to develop and deepen skills through continuous learning and a growth mindset
• Demonstrated ability to drive innovation and adopt emerging tools and methodologies
• Transistor-level layout knowledge using tools such as Cadence Virtuoso, and design languages like SKILL
• Demonstrated ability to contribute and collaborate effectively within diverse teams
• Knowledge of quantum computing