AppLab Systems, Inc is seeking an ASIC Verification Engineer to enhance their verification processes and deliver high-quality IP blocks. The role involves defining formal verification plans, reviewing RTL design architecture, and ensuring functional correctness for complex hardware systems.
Responsibilities:
- Define formal verification plans for hardware systems
- Review RTL design architecture and specifications
- Prove functional correctness using formal methods
- Deliver formal sign-off for IP blocks
- Develop and maintain verification regressions and tools
- Integrate formal and functional verification methodologies
Requirements:
- 5+ years using model checking in production, achieving 100% functional correctness
- 5+ years using logical equivalence checking in production, achieving 100% functional correctness
- Proficient in Verilog and System Verilog in production, with 10+ projects
- Proficient in scripting languages (Tcl, Python, Perl) in production, with 5+ scripts
- Experience debugging complex ASIC designs (CPU, GPU, NOC) in production, with 3+ projects
- Degree in Electrical Engineering, Computer Science, or equivalent
- Experience with interactive theorem proving (1+ project)
- Knowledge of advanced computer architecture concepts (2+ years)
- Familiarity with PCIE and Ethernet protocols (1+ project)
- Experience with formal verification tools (e.g., Cadence, Synopsys) (1+ year)
- Experience in a team of 5+ engineers on verification projects