Principal RTL Lead – High-Speed Ethernet (ASIC)

Introduction:

We are seeking an experienced Principal RTL Lead to drive the design and verification of next-generation Ethernet subsystems for custom ASIC silicon. This role is central to building architectures that support 400G, 800G, and beyond, enabling ultra-low latency and high reliability in large-scale data centers. As the technical lead, you will guide a team of designers through complex challenges such as multi-lane alignment, Forward Error Correction (FEC), and advanced clocking, while ensuring seamless integration of Ethernet IP into ASIC designs.

Responsibilities:

• Technical Leadership: Act as the primary architect for the Ethernet subsystem. You''''''''ll define micro-architecture for high-bandwidth data paths and complex control logic.
• Protocol Mastery: Own the implementation of IEEE 802.3 standards, including RS-FEC (254, 256), multi-lane distribution (MLD), and auto-negotiation/link training (AN/LT).
• High-Speed Logic Design: Solve the hard problems of networking: managing massive bus widths (e.g., 1024-bit+), minimizing logic depth for timing closure, and handling complex CDC across asynchronous boundaries.
• Front-End Integration: Lead the integration of third-party SerDes IP and ensure seamless interoperability between the electrical physical layer and the digital MAC.
• Design for Excellence: Drive best practices in coding (SystemVerilog), power optimization (UPF), and lint/CDC/RDC analysis to ensure first-pass silicon success.
• The Track Record: 10+ years of experience in RTL design with at least 3-4 successful tape-outs in advanced process nodes (7nm, 5nm, or 3nm).
• Ethernet Expertise: Deep, hands-on experience with 100G/400G/800G Ethernet protocols and the underlying sub-layers (MAC, PCS, FEC).
• ASIC Lifecycle: Expert knowledge of the full front-end ASIC flow—from architectural spec to synthesis, formal verification, and post-silicon bring-up.
• High-Speed Design: Proven ability to close timing on high-frequency designs and manage complex clocking architectures.
• Scripting Power: Proficiency in Python or Perl for creating sophisticated design-generation and analysis tools.

Requirements:

Required Skills: ASIC, Change Data Capture, Computer Hardware, Data Centers, Ethernet, Logic Synthesis, Management, Scripting, Training, Timing Closure.

Preferred Skills:

• Experience with IEEE 1588 (PTP) hardware stamping for precision timing.
• Familiarity with CXL or PCIe Gen 5/6 protocols.
• Direct experience working with physical design teams on timing and congestion mitigation.