FPGA Verification Engineer - UVM / Emulation

Quest Defense Systems & Solutions is seeking a Senior FPGA Verification / UVM Architect to lead the development of a scalable simulation and emulation environment for safety-critical FPGA systems. This role focuses on building and optimizing UVM-based verification environments while providing technical leadership across FPGA programs.

Responsibilities:

• Architect and develop SystemVerilog/UVM-based verification environments for FPGA designs
• Build scalable, reusable testbench infrastructure (agents, monitors, scoreboards, predictors)
• Define verification strategies, including sequences, constraints, and coverage models
• Develop and enhance simulation environments to support block and full-chip verification
• Leverage Siemens Veloce (or similar emulation platforms) to accelerate verification and debug
• Integrate simulation and emulation workflows for complex FPGA systems
• Support high-speed interface validation (e.g., MV3 or similar protocols where applicable)
• Ensure verification activities align with DO-254 DAL A/B objectives
• Develop and review verification artifacts, including:
• Test plans, procedures, and cases
• Requirements traceability matrices
• Coverage and verification reports
• Participate in design and verification reviews (PDR/CDR/VER)
• Assess and improve existing UVM environments, identifying gaps and inefficiencies
• Provide guidance to distributed teams on UVM best practices and verification strategy
• Support coverage closure (functional, code, assertion, FSM) and debug complex issues
• Act as a technical lead/SME across FPGA verification efforts

Requirements:

• Bachelor's/Master's in Electrical Engineering or related field
• 10+ years' experience in FPGA/ASIC verification
• Strong experience working in DO-254 environments (DAL A/B preferred), including requirements-based verification, traceability, and certification support
• Deep expertise in SystemVerilog and UVM, including:
• Architecture and development of scalable UVM testbenches (block and top-level)
• Development of advanced UVM components (agents, monitors, scoreboards, predictors, sequences, register models)
• Coverage-driven verification and closure strategies
• Experience with UVMF or reusable verification frameworks and ability to lead or coordinate teams developing shared testbench environments
• Experience performing technical reviews, audits, or compliance assessments, including review of:
• Verification plans and strategies
• UVM testbench architecture
• Coverage models and metrics
• Requirements traceability and test results
• Direct experience with Siemens Veloce (or similar emulation platforms) for FPGA verification
• Familiarity with MV3 (Merge Version 3) protocol or similar high-speed communication protocols used for interfacing with graphics or display engines (i.e., GE5)
• Strong RTL debug and simulation experience, including identifying and resolving issues in testbench implementation, interfaces, and data/control paths
• Familiarity with tools such as QuestaSim and modern simulation/verification workflows
• Strong communication skills for delivering findings and corrective-action recommendations
• Self-motivated, proactive, and comfortable with remote collaboration
• Code coverage analysis for RTL Source (Statement, Branch, Focused Expression and Condition Coverage)
• Experience supporting board bring-up and HW/SW integration
• Experience generating or reviewing DO-254 lifecycle documents
• Experience with FAA/EASA SOI Audits
• Experience with FPGA Validation on Target Hardware and/or creating automated test scripts for performing requirements-based testing on target hardware
• Experience in using lab tools like Oscilloscope and Logic Analyzer with a good understanding of FPGA timing