VLSI CAD Engineer

Bachelor or above Degree in Electrical Engineering, Computer Engineering, Physics Engineering or related field with experience in VLSI chip development or semiconductor technology

Experiences with Cadence design automation infrastructure development (SKILL, Python or Perl scripting)

Experiences with Cadence SKILL programming language and/or related languages (Python and/or Perl, etc), at least 3 years.

Familiarity with layout verification tools from Cadence Pegasus, Synopsys ICV, or Siemens Calibre, including design rule checking (DRC) with 3+ years of relevant experience

Strong understanding of Linux environments and shell scripting with a minimum of 2+ years of experience

Strong understanding of physical layout and technology ground rules

Ability to debug errors and solve problems in a team environment

Strong experience using the Cadence Virtuoso layout design tool, at least 5 years

Experiences with Cadence SKILL programming language for Pcell Development & Design Automation, at least 3 years

Experience with Cadence Virtuoso automated layout design tools, at least 2 years

Experience with Cadence techfile/mapfile creation or updates is a great plus

Experience with version control systems such as Git and familiarity with collaborative software development workflows (e.g., GitHub, GitLab, or Bitbucket)

Experienced user of Synopsys ICV DRC checking tool

Experience with advanced sub-micron semiconductor technology nodes