Tech Lead Field Application Engineer

Astera Labs is a provider of rack-scale AI infrastructure through purpose-built connectivity solutions. The Tech Lead Field Application Engineer will act as the technical bridge between customers and engineering teams, supporting connectivity solutions and helping design, validate, and deploy silicon into AI infrastructure systems.

Responsibilities:

• Serve as the primary technical point of contact for strategic customers, providing deep application support for Aries, Scorpio, and Leo product families
• Drive board design reviews, schematic reviews, and system-level debug sessions with customer hardware and system development teams
• Deliver technical presentations, training sessions, and product demonstrations tailored to customer architectures and use cases
• Lead hands-on debug of PCIe, Ethernet, and CXL/DDR memory connectivity issues in customer server and rack-scale platforms
• Collaborate with internal silicon, firmware, and applications engineering teams to resolve field issues and drive root cause analysis
• Develop and maintain application notes, reference designs, and technical collateral based on field learnings
• Capture and communicate customer requirements, competitive insights, and system architecture trends to product management and engineering
• Represent the voice of the customer in internal roadmap discussions, helping shape next-generation connectivity solutions
• Identify new use cases and expansion opportunities within existing accounts

Requirements:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in server hardware design, cloud system development (SysDev), or field application engineering
• Hands-on experience with PCIe protocol/physical layer including signal integrity fundamentals, link training, and debug
• Working knowledge of DDR memory subsystems and memory interface design or validation
• Self-starter mentality with the ability to work independently and drive customer engagements with minimal supervision
• Willingness to travel up to 40-50% to customer sites
• Experience with CXL protocol or CXL-enabled memory architectures
• Familiarity with Ethernet switch or NIC silicon in data center environments
• Experience working directly with hyperscaler or Tier-1 OEM customers
• Proficiency with lab equipment (oscilloscopes, protocol analyzers, BERT) and signal integrity tools
• Strong presentation and communication skills with the ability to convey complex technical concepts to diverse audiences
• Prior experience at a semiconductor company in an FAE or applications engineering capacity