Senior ASIC Design Verification Engineer

Ethernovia is developing innovative Ethernet-based networks for software-defined and autonomous vehicles, robotics, and other intelligent machines. The Senior ASIC Design Verification Engineer will be responsible for all aspects of digital SoC verification, collaborating with architects, designers, and software engineers to validate advanced automotive communication semiconductors and systems.

Responsibilities:

• Responsible for all aspects of digital SoC verification
• Work with architects, designers, and SW engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems
• Contribute to a positive, trusting, and cohesive working environment based on integrity and strong work ethics

Requirements:

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC verification experience
• Strong understanding of ASIC verification fundamentals and industry standard methodologies
• Experience with Verilog/System Verilog, UVM, Python, TCL, C/C++
• Experience with the full verification flow, from spec to coverage analysis to gate level sim
• Debugging failures in simulation to root cause problems
• Self-motivated and able to work effectively both independently and in a team
• Excellent communication/documentation skills
• Attention to details
• Collaboration across multidisciplinary and international teams
• Experience in Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• Third party IP (SerDes, controllers, processors, etc.)
• Modular and Reusable Testbench architecture
• Design for re-use of pre and post silicon tests and infrastructure
• Automation of testbench creation, tests, regression, or EDA tools
• Knowledge of SystemC and/or DPI