Key skills
CUDA kernel designMemory hierarchy optimizationRegister pressure managementHBM bandwidth planningGPU code developmentReal-time system designMulti-device GPU systemsNVLinkNIC/RDMABandwidthlatency accountingOFDM signal processing5G NR physical layerChannel emulationGPU-accelerated numerical workloadsHigh-performance computingComputer architectureSignal processingWireless communications
About this role
NVIDIA is seeking a self-motivated senior engineer for the Aerial Omniverse Digital Twin team. This role involves designing and implementing real-time signal-processing subsystems for large-scale GPU systems, contributing to foundational technology for 5G and 6G network simulation.
Responsibilities:
- Design and implement GPU kernels that apply time-varying, multi-antenna channels to OFDM signals under hard real-time deadlines
- Architect the inter-cell data-flow layer to ensure efficient information transfer within NVLink and NIC budgets at scale
- Work with propagation engine and RAN stack teams to orchestrate the end-to-end simulation pipeline, ensuring synchronization across hundreds or thousands of GPUs
- Assess design and implementation trade-offs between physical fidelity, latency, and system scalability
Requirements:
- PhD in high‑performance computing, computer architecture, signal processing, or wireless communications (or equivalent experience)
- 12+ years of proven experience
- Proficiency in CUDA kernel design with attention to memory hierarchy, register pressure, and HBM bandwidth planning, with a track record of writing production‑quality GPU code that meets hard real‑time deadlines
- Demonstrated ability to build and reason about data flows across multi‑device GPU systems (NVLink, NIC/RDMA) with explicit bandwidth and latency accounting
- Working knowledge of OFDM signal processing and the 5G NR physical layer, sufficient to implement and validate a channel‑emulation pipeline
- Impactful publications involving GPU‑accelerated numerical workloads or real‑time system design
- Experience with GPU‑accelerated RAN platforms, L1/L2 software stacks, or channel emulators
- Knowledge of high‑bandwidth GPU interconnects (NVLink, NVSwitch) and their scaling properties
- Familiarity with massive MIMO beamformer design and MU‑MIMO precoding