Principal Electrical Engineer FPGA/ASIC (Remote)

Collins Aerospace is a leader in technologically advanced, intelligent solutions that help redefine the aerospace and defense industry. The Principal Electrical Engineer FPGA/ASIC will be responsible for the design, implementation, verification, and integration of high-performance ASICs, FPGAs, and SoPCs for Collins Avionics solutions.

Responsibilities:

• Requirements capture, decomposition, and traceability
• FPGA/ ASIC/SoPC digital architecture development and design
• Develop RTL design code and simulation in VHDL, Verilog, and/or SystemVerilog
• Create UVM constrained random environments using SystemVerilog
• Create placement and timing constraints
• Perform synthesis, place and route
• Perform static timing analysis, linting analysis, LEC, and clock-domain-crossing analysis
• Perform FPGA/ ASIC/SoPC verification using inspection, analysis, simulation, and test methods
• Creation of DO-254 DAL-A certification artifacts for Airborne Electronic Hardware (AEH)
• Conduct and/or participate in peer reviews throughout product lifecycle
• Participate in FAA SOI audits
• Create engineering bids and support RFIs and RFPs
• Communicate well with a wide variety of individuals including Engineering, Program Management, internal leadership and customers
• May lead a team of engineers and/or perform the duties of a project engineer
• Recommend new tools and practices for continuous improvement in the group’s FPGA/ ASIC design flow
• Provide guidance or mentor other engineers with a variety of skills and backgrounds

Requirements:

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field
• Proficient writing RTL and/or testbenches using VHDL, Verilog, or SystemVerilog
• Proficient with Linux (or Unix), scripting, C/C++, Python, and/or Perl
• Proficient using FPGA specific tools (e.g. Questasim, Vivado, Libero, Synplify Pro, etc.)
• Experience with data interfaces (PCIe, DDR, I2C, Ethernet, CDN, ARINC-429, etc.)
• Experience with device level timing and clock domain crossing
• Ability to work with minimal supervision, as part of a team of engineers with a variety of skills and backgrounds, located throughout the world and matrixed into projects with aggressive schedules and frequent milestones
• Experience with UVM Constrained Random Methodology
• Proficient with DO-254 design assurance activities for ASIC, FPGA, and/or SoPC developments
• Experience with video and/or networking concepts and architectures
• Proficient with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, code coverage, LEC, SystemVerilog)
• Experience successfully managing cost, schedule, and performance objectives
• Experience with risk management (identify, quantify, and mitigate risks)