Key skills
PythonCAzureCI/CDLeadershipCollaboration
About this role
Overview
Responsibilities
Qualifications
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for a Principal Signoff CAD Engineer to help achieve that mission.
As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Methodology, Infrastructure, Silicon Engineering, and Labs engineering (MILE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for a Principal Signoff CAD Engineer with a passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.
We are looking for a Principal Signoff CAD Engineer specializing in silicon signoff to join the team. In this role, you will own the signoff CAD strategy and flow architecture across parasitic extraction, static timing analysis, power integrity, and physical verification for Microsoft’s next-generation silicon programs. You will bring experience across the full signoff tool ecosystem—including StarRC/Pegasus, PrimeTime/Tempus, Redhawk-SC/Voltus, and Fusion Compiler/Innovus—and a record of driving quality, growth, and technical leadership at scale.
Responsibilities
- Own and architect the end-to-end silicon signoff CAD flow strategy across parasitic extraction (StarRC/Pegasus), static timing analysis (PrimeTime/Tempus), power integrity and IR-drop analysis (Redhawk-SC/Voltus), and physical verification, ensuring production-quality convergence for advanced-node silicon programs.
- Drive deep quality improvements across signoff methodologies by establishing best practices, defining quality metrics, and implementing systematic validation frameworks that prevent silicon escapes and reduce re-spins.
- Lead technical engagement with EDA vendors (Synopsys, Cadence) to evaluate, qualify, and deploy new signoff tool versions; drive resolution of critical tool issues and influence vendor roadmaps to align with Microsoft’s silicon development needs.
- Collaborate with physical design construction teams and front-end RTL teams to ensure seamless integration between implementation and signoff, driving convergence of timing, power, and physical verification closure across multiple concurrent silicon programs.
- Grow the signoff engineering team by establishing technical standards, conducting design reviews, and fostering a culture of continuous improvement; serve as the technical authority for signoff decisions and trade-offs across the organization.
Qualifications
Required Qualifications:
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Other Requirements:
- Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
- This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.
Preferred Qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field AND 10+ years of experience in silicon signoff CAD engineering, OR Master’s degree AND 8+ years of equivalent experience.
- 10+ years of hands-on experience with parasitic extraction tools (Synopsys StarRC and/or Cadence Pegasus) and static timing analysis tools (Synopsys PrimeTime and/or Cadence Tempus) in advanced process nodes (5nm and below).
- 10+ years of familiarity with physical design implementation tools (Synopsys Fusion Compiler and/or Cadence Innovus).
- Good scripting and automation experience in TCL and Python for developing production signoff flows and infrastructure.
- Experience leading signoff convergence on multiple concurrent tapeouts at 5nm or below with track record of zero-escape silicon quality.
- Experience working across both Synopsys and Cadence tool ecosystems with the ability to evaluate competitive solutions and drive best-in-class tool selection decisions.
- Record of driving technical growth in teams, and establishing reusable flow architectures that scale across multiple silicon programs.
- Experience working on geographically distributed teams with good collaboration skills; familiarity with cloud-based EDA compute environments and modern CI/CD practices for CAD flow development.
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Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
https://careers.microsoft.com/us/en/us-corporate-pay
This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.
Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.