Senior Manager, ASIC Design Engineering

Cornelis Networks is building the future of AI and HPC networking with an AI-first approach to silicon and software development. They are seeking a Senior ASIC Design Engineering Manager to lead and grow their RTL design engineering team, managing full-lifecycle development of high-performance networking ASICs and driving organizational strategy for a world-class design team.

Responsibilities:

• Own ASIC RTL delivery schedules across major milestones by tracking, monitoring, and reporting progress against committed plans
• Utilize data-driven insights to predict schedule risks and proactively reallocate human resources to keep the project on track
• Align RTL delivery schedules with DV and emulation enablement and manage feedback loops and dependencies efficiently
• Facilitate physical design handoffs by ensuring design teams provide high-quality RTL and constraints that minimize timing-closure iterations. Track physical design feedback and delivery schedules to support physical design signoff and tape-out milestones
• Lead long-term headcount planning and organizational design for the ASIC department. Identify skill gaps and execute global talent acquisition strategies that support the product roadmap

Requirements:

• 15+ years in the semiconductor industry, preferably in high performance designs on advanced technology nodes, with at least 5 years in people management
• B.S. or M.S. in Computer Engineering, Electrical Engineering, or related technical field, or equivalent practical experience
• Deep understanding of the interaction between Design, Verification, Emulation, and Physical Design teams. You must know 'how the work gets done' to manage the people doing it
• Proven ability to lead large engineering organizations through multiple full-cycle ASIC product launches in a remote environment. Ability to coordinate across multiple projects, manage risks and escalations, and work under tight schedules and budget constraints
• Strong technical expertise in microarchitecture development, RTL coding (Verilog/System Verilog), synthesis, STA/timing closure, physical design, and verification methodologies
• Exposure to one or more industry standards/protocol stacks such as PCIe, Ethernet, UCIe, UALink
• Demonstrated ability to optimize designs for PPA (power, performance, area) and to integrate major subsystems (interconnect, I/O, memory)
• Exposure to AI based design implementation and verification flows, scripting for automation, milestone tracking and flow integration
• Experience building globally distributed ASIC design teams and scaling engineering practices in a remote environment