leading development of DFT solutions for next-generation ASICs
Lead implementation of SSN, hierarchical test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST
Generate and deliver ATPG test pattern for stuck-at, transition, cell aware and path delay fault models
drive scan-based diagnosis methodology for Silicon failure debug
provide post-silicon testing and validation support
evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
Perform simulation runs and debug for non-timing and back annotated timing (SDF) gate level simulations
Develop test scripts, automate processes, and analyze data using programming languages such as Python, Tcl, or C++

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
Prior experience working with ASICs
Prior experience in scan insertion and DFT setup, integration and validation
Prior experience implementing DFT architectures—including scan insertion, compression/decompression logic, and memory/logic BIST.
10+ years of experience working with ASICs (preferred)
10+ years of experience in scan insertion and DFT setup, integration and validation (preferred)
Experience driving ASIC DFT execution from concept through tapeout (preferred)
Experience working with ATE testers and test teams (preferred)
RTL experience to understand and debugging issues pertaining to DFT (preferred)
Ability to solve complex problems including clock domain crossings (preferred)
Familiar with advanced silicon process and technology nodes for high speed and low power consumption (preferred)
Strong implementation or integration of design blocks using Verilog/System Verilog (preferred)

ASIC Engineering Technical Lead – DFT

Key skills