Synopsys IncRemote
Hardware Engineering, Architect-17965
United States of America
Full Time
4 hours ago
H1B Sponsor Likely
Key skills
DDR/HBM SIPI engineeringHigh-speed interface signalingS-parametersChannel loss analysisCrosstalk analysisEqualization techniquesJitter analysisPower delivery modelingSignal integrity analysisPower integrity analysisEye diagram constructionStatistical modelingReturn loss analysisImpedance matchingResonant system analysisHFSSAnsys toolsHSPICERaptorADSBoard-level constructionOn-chip IO designIssue resolutionPerformance OptimizationCommunication
About this role
Synopsys Inc is a leader in chip design and verification technology, and they are seeking a seasoned Hardware Engineering Architect. The role involves performing assessments and optimizations for high-speed interface designs while ensuring effective communication with design teams and customers.
Responsibilities:
- Perform interconnect assessments using the latest modeling techniques to predict channel data rates and signal margins
- Assess strategies for system performance optimization, including signal margins, power, and FFE, DFE, and CTLE equalization techniques
- Assess power delivery systems to optimize power integrity for supply stability and jitter minimization
- Document findings in reports and design guidelines
- Communicate results and insights to design teams to improve PHY design
- Communicate results and recommendations to customers to enable them to optimize their system performance
- Interact with design teams and customers to refine and apply signal and power analysis methods to refine strategies and address problems
- Understand Synopsys’ DDR and HBM PHY roadmap and create strategies for improved performance
- Track industry developments through activities at standards committees and through memory vendor roadmaps
Requirements:
- Over 15 years of experience in DDR/HBM SIPI engineering
- Deep understanding of high-speed interface signaling operations, including s-parameters, channel loss, crosstalk, equalization techniques, jitter, and power delivery modeling
- Expertise in signal and power integrity analysis methods, such as eye diagram construction through statistical modeling, return loss, impedance matching, and resonant system analysis
- Proficient in using HFSS and Ansys tools, HSPICE, Raptor, and ADS
- Skilled at generating and communicating results, findings, conclusions, and recommendations within a design team and to external customers
- Knowledge in board-level construction and on-chip IO design operation
- Ability to track industry developments through activities at standards committees and memory vendor roadmaps
- Ability to communicate clearly and efficiently
- Ability to independently lead issues to full closure