Senior Mask Design Engineer – Hardware

NVIDIA develops GPUs and SOCs focused on power, performance, and efficiency, and is seeking a Senior Mask Design Engineer. The role designs and develops detailed layouts of silicon interposers, collaborates with package and design teams, and addresses scheduling, cost, manufacturing, and electrical design issues.

Responsibilities:

• You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule
• Performing physical layout for silicon interposer using Cadence tools
• Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance
• Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists
• Propose layout design trade-offs to the PTL for resolution and implementation

Requirements:

• Hold a B.S. Electrical Engineering or equivalent experience
• Minimum of 5+ years proven experience in Mask and Layout Design
• Deep understanding of layout concepts in submicron CMOS technologies
• You are an authority with Cadence layout tools - particularly Virtuoso
• Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc
• Proficient in scripting languages like Perl, Python, Skill, etc
• Should have knowledge of DRC and LVS checking flows, ability to customize decks
• You can work optimally in a team, good interpersonal skills, passion and positive energy
• Knowledge of Integrity auto-routing is a plus
• Knowledge of APD package layout tool is a plus
• Good understanding of packaging technology is useful