Job Title: Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration
Location :San Jose, CA - Relocation is Fine MST AND PST
Job Summary
We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with Architecture, RTL, Verification, DFT, Physical Design, STA, and Silicon Validation teams.
The ideal candidate should possess deep expertise in PCIe protocol, high-speed interfaces, subsystem integration, timing closure methodologies, and full ASIC development flow from architecture through silicon bring-up.
Key Responsibilities
Lead development and integration of PCIe Gen5/Gen6 Controller, PHY, and SerDes subsystems.
Define subsystem architecture, interface specifications, microarchitecture, and design documentation.
Participate in Transaction Layer development and enhancements.
Support PCIe/CXL interoperability and advanced features.
Drive integration of high-speed PHY and SerDes IPs.
Work on:
Link training
Equalization
PLL integration
Reference clock architecture
PIPE interfaces
Lane repair and lane aggregation
Collaborate with analog and PHY teams during integration and debug.
Work closely with DV teams to:
Define comprehensive verification plans.
Review UVM-based test environments.
Develop assertions and coverage metrics.
Support protocol compliance testing.
Debug simulation, emulation, FPGA, and post-silicon issues.
Support DFT implementation including:
Scan insertion
MBIS
LBIST
JTAG/Boundary Scan
At-speed testing
Define test requirements for PCIe controller and PHY subsystems.
Collaborate with DFT and silicon validation teams to achieve coverage target
Develop and maintain subsystem-level SDC constraints for:
Synthesis
Static Timing Analysis
Place & Route
Timing signoff
Work with PD and STA teams to achieve timing closure
Silicon Bring-Up & Debug
Support:
PCIe link training debug
Compliance testing
Silicon characterization
Performance tuning
Analyze protocol traces and lab debug logs.
