About this role

Job Title: Principal / Lead Engineer
Location: San Jose, CA

Job Summary:

We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development,
integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-
based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities,
contribute to Transaction Layer development, and work closely with Architecture, RTL, Verification,
DFT, Physical Design, STA, and Silicon Validation teams.
The ideal candidate should possess deep expertise in PCIe protocol, high-speed interfaces,
subsystem integration, timing closure methodologies, and full ASIC development flow from
architecture through silicon bring-up.

Key Responsibilities:

Lead development and integration of PCIe Gen5/Gen6 Controller, PHY, and SerDes
subsystems.
Define subsystem architecture, interface specifications, microarchitecture, and design
documentation.
Participate in Transaction Layer development and enhancements.
Support PCIe/CXL interoperability and advanced features.
Drive integration of high-speed PHY and SerDes IPs.
Work on:
Link training
Equalization
PLL integration
Reference clock architecture
PIPE interfaces
Lane repair and lane aggregation
Collaborate with analog and PHY teams during integration and debug

Work closely with DV teams to:

Support DFT implementation including:

Support:

Education:

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or
related discipline. With 10+ years of experience
Masters degree preferred for Principal Engineer role.