Physical Design Engineer

Job Title: Physical Design Engineer

Location: Mountain View, CA (Onsite)

We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs.

Key Responsibilities:

1. Own Netlist-to-GDSII for high-speed, low-power SOC

2. Floorplanning, Placement, CTS, Routing, Timing closure

3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm

4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc

5. Hands on experience on tools - Synopsys Fusion Compiler, Innovus, Primetime, Calibre

Very Imp Skill : Innovous, 2nm, 3nm, 4nm, 5nm