Senior ASIC RTL Design Engineer, AI Hardware

Cerebras Systems builds high-performance AI semiconductor hardware, including the Wafer Scale Engine. The company is seeking a Senior ASIC RTL Design Engineer to lead RTL design and integration for next-generation wafer-scale processors, collaborating with verification, physical design, software, and systems teams to deliver high-performance, power-efficient products.

Responsibilities:

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis
• Work closely with PD team members for design closure to meet PPA goals
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product
• Debug silicon-level functional, timing, and power issues during bring up

Requirements:

• Master's degree in Computer Science, Electrical Engineering, or equivalent
• Can work in a hybrid work environment
• 8+ years of experience in delivering complex, high performance high quality RTL designs
• Experience with Front End Chip integration and third-party IP integration
• Demonstrated experience in high-performance computing, GPU/CPU designs, machine learning or related fields
• Proven track record of multiple silicon success
• Experience collaborating with external vendors
• Networking stack experience including TCP/IP, RDMA and Ethernet
• Knowledge of PCIe, CPU interfaces and Serdes technology
• Working knowledge of scripting tools : Python, TCL
• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus
• Experience managing external ASIC vendor through product development cycle