ASIC Engineering Technical Leader

Role: ASIC Engineering Technical Leader

Location: San Jose, CA (Onsite)

Start Date: Immediate

Type: Contract (C2C/W2)

Interview: Phone/Video

We are seeking an ASIC Engineering Technical Leader with strong expertise in DesignforTest (DFT) for nextgen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gatelevel simulations, and automation using Python/Tcl/C++.

Qualifications:

• BS + 8 yrs / MS + 6 yrs / PhD + 3 yrs experience

• Proven background in ASICs, DFT setup, scan insertion, and validation

• Handson with Siemens Tessent, ATPG, Memory/Logic BIST

• Strong scripting (Python/Tcl/C++) and RTL debugging skills

Preferred:

• 10+ yrs ASIC/DFT experience, SSN expertise, ATE tester exposure

• Verilog/SystemVerilog integration, advanced silicon process knowledge

Gaurav

PDDN Inc., Fremont, CA

Phone:

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