Design Verification Engineer - Contractor

Verilab is seeking an experienced verification engineer for a contract engagement supporting its clients with verification services. The role contributes to verification planning and implementation, develops verification environments, resolves technical challenges, and helps achieve project milestones and verification closure in collaboration with Verilab consultants and client engineering teams.

Responsibilities:

• As a contractor, you will contribute your expertise to verification planning and implementation, with responsibilities defined by the scope of the engagement
• You will develop robust verification environments, address complex technical challenges, and help achieve project milestones and verification closure
• You will collaborate with Verilab consultants and client engineering teams, bringing technical insight, clear communication, and ownership of your deliverables

Requirements:

• BSc/MSc in Electronic Engineering, Computer Engineering, or Computer Science
• At least 7 years of project-proven verification experience
• Strong SystemVerilog/UVM development experience, including:
• Block and integration level verification
• Development of coverage driven, self-checking verification environments from scratch
• High level sequence based stimulus
• Complex transaction based checkers, including scoreboards with data translation and ordering
• Register models
• Specification level checks for protocols such as AXI, DDRx, PCIe, and USBx
• Demonstrated verification planning experience, including:
• Requirements capture and traceability
• Effort estimation and prioritization
• Use of metrics to assess progress and determine verification closure
• Ability to take ownership of agreed deliverables, from planning through implementation
• Experience meeting demanding project deadlines and resolving technical challenges
• Effective communication and collaboration with consultants, clients, and engineering teams
• All candidates must be a US person (citizen or permanent resident)