Formal Verification Engineer - Professional Level

LUBIS EDA hires a Formal Verification Engineer to deliver end-to-end formal verification work for semiconductor designs. The role owns verification scope, strategy, execution, proof closure, and customer-ready sign-off artifacts while collaborating with designers and stakeholders.

Responsibilities:

• Own a block/area: clarify requirements, co-define the verification strategy (scope, risks, approach), execute, and close
• Produce maintainable SVA and a clean formal environment (constraints/assumptions with good hygiene)
• Debug efficiently, partner with designers on fixes, and prevent regressions
• Keep stakeholders aligned with crisp updates and decision-ready evidence

Requirements:

• Proven experience delivering formal results on non‑trivial RTL (e.g., caches, pipelined processors, DMAs, NoCs)
• Strong SVA skills and hands-on formal tool experience (e.g.: Jasper, VCF, Questa Formal/Onespin)
• Reliable end‑to‑end ownership in a defined scope