Principal Embedded Firmware Engineer — AI/HPC Networking Silicon

Cornelis Networks develops high-performance fabric solutions for AI and HPC. The Principal Embedded Firmware Engineer will architect and develop management firmware for next-generation networking silicon, including secure firmware loading, engine bring-up, and platform-level embedded architecture, while providing technical leadership and mentorship.

Responsibilities:

• Architect and implement bare-metal C firmware on a RISC-V management core that provisions, boots, and supervises arrays of on-chip acceleration engines
• Own the secure firmware-loading pipeline: fetch images from flash, coordinate hardware root-of-trust authentication, and distribute verified images into each engine's local memories through on-chip fan-out/DMA hardware
• Build per-engine bring-up, reset sequencing, and health validation driven by control/status registers, with solid timeout and error handling and enforced security invariants
• Scale firmware distribution and bring-up across many engines and multiple dies, including runtime re-boot and in-field firmware updates
• Define the hardware/software contract with ASIC/RTL teams using a datamodel-first workflow (e.g., SystemRDL, Kaitai, YAML → generated code)
• Validate firmware against functional simulators (e.g., QEMU) with automated unit and integration tests
• Set architecture standards, review designs and code, and mentor engineers

Requirements:

• 10+ years of embedded/firmware engineering, with a track record of software architecture and technical leadership
• Expert C (C++ a plus) and working Python
• Deep experience with bare-metal firmware on constrained cores, including manually managed local memories and low level bring-up
• Experience with secure boot / image authentication and hardware root-of-trust integration
• Experience programming hardware CSRs and co-designing register-level interfaces with silicon teams
• Demonstrated, hands-on AI-assisted engineering proficiency, plus the judgment to validate what the AI produces
• RISC-V firmware and toolchain experience
• Firmware orchestration for multi-core accelerator arrays
• Hardware root-of-trust ecosystems (e.g., Caliptra) and SHA-2/signature verification
• Code-generation toolchains (SystemRDL, Kaitai, CMake) and simulator-based co-verification
• Familiarity with emerging AI/HPC interconnect standards: Ultra Ethernet (UEC), UALink, and ESUN
• Background in HPC/AI networking, RDMA, or libfabric