Top Level Integration Engineer

Job Description

Title: Top Level Integration Engineer
Location: Onsite 5 days in San Jose, CA

Looking for: Senior semiconductor physical design engineer responsible for integrating individual chip blocks into a complete chip layout, managing bump/RDL routing, resolving DRC/LVS violations, and driving full-chip physical verification through tapeout.

Must-Have Skills
- Full-Chip Physical Integration: Hands-on experience combining multiple GDS/OASIS blocks into a complete chip layout.
- GDS/OASIS: Hierarchical layout assembly, integration, and connectivity verification.
- Bump/RDL Routing: Bump placement, assignment, redistribution layer routing, and chip-package interface.
- DRC/LVS Signoff: Full-chip physical verification, debugging, and violation closure.
- EDA Tools: Cadence Innovus, Siemens Calibre, Synopsys IC Validator, or equivalent.
- Tapeout Experience: Foundry design rules, final GDS/OASIS deliverables, and signoff.
- Independent Ownership: Ability to own full-chip integration from assembly through tapeout without extensive supervision.