Hiring: Physical Design Engineer
We are looking for an experienced Physical Design Engineer to work on advanced technology nodes and high-performance IP designs.
Key Responsibilities
- Execute RTL-to-GDSII implementation, including synthesis, place and route, timing optimization, and physical verification.
- Perform floorplanning, Clock Tree Synthesis (CTS), clock gating, and buffer/repeater insertion.
- Optimize designs for Power, Performance, and Area (PPA).
- Support scan stitching, logic equivalence checking, and timing/electrical signoff.
- Develop and improve physical design methodologies and automated design flows.
- Collaborate with cross-functional and geographically distributed teams.
Required Skills
- Strong experience in Physical Design and RTL-to-GDSII implementation.
- Proficiency in Synopsys ICC2, Fusion Compiler, PrimeTime, and Calibre.
- Experience with synthesis, timing-driven place and route, CTS, and physical verification.
- Strong understanding of STA, timing closure, PPA optimization, and digital circuit design.
- Verilog knowledge and experience with high-speed datapath, control logic, or high-performance IP designs.
Education & Experience
- Bachelor's degree in EE, ECE, CS, or a related field with 5+ years of experience; OR
- Master's degree in a relevant field with 3+ years of experience.
- Experience with high-speed, multi-gigabit SerDes PHY or other high-performance IP designs is preferred.
Interested candidates, please share your updated resume or DM me for further details.
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