IP / SoC Design Verification Engineer

SVT IT INFOTECH is seeking an IP / SoC Design Verification Engineer to verify complex IP and System-on-Chip designs using functional and formal verification methodologies. The role develops verification environments, runs simulation-based tests, debugs RTL issues, and collaborates with design and architecture teams to ensure design functionality, reliability, and quality.

Responsibilities:

• Develop and execute verification plans for IP-level and SoC designs based on functional specifications
• Design, implement, and maintain scalable testbenches using SystemVerilog and UVM methodology
• Perform functional and formal verification of RTL designs to ensure specification compliance
• Develop directed and constrained-random test cases to validate functional scenarios and corner cases
• Execute simulation, regression, and coverage-driven verification activities
• Debug simulation failures, analyze waveforms, and identify root causes of design issues
• Develop and maintain assertions, functional coverage models, and code coverage metrics
• Create reusable verification components, environments, and Verification IP (VIP)
• Perform IP-level and SoC integration verification for protocols such as AXI, AHB, APB, and PCIe
• Collaborate with RTL designers, architects, and integration teams to resolve bugs and improve design quality
• Utilize EDA tools from Synopsys, Cadence, and Siemens for simulation, verification, and debugging
• Develop scripts using Python, Perl, or Shell to automate verification workflows
• Review RTL implementations and verification results to ensure design readiness and quality

Requirements:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics, or a related discipline
• Strong understanding of digital logic design, RTL design, and computer architecture fundamentals
• Knowledge of functional verification and formal verification concepts
• Hands-on experience or academic project exposure to SystemVerilog and UVM
• Familiarity with testbench development, simulation, and regression testing
• Understanding of constrained-random verification, assertions, and functional coverage
• Knowledge of IP design, SoC architecture, and standard protocols such as AXI, AHB, APB, or PCIe
• Familiarity with RTL debugging, waveform analysis, and EDA verification tools
• Basic scripting knowledge in Python, Perl, or Shell
• Strong analytical, problem-solving, communication, and teamwork skills
• Experience or academic project exposure in IP-level or SoC design verification
• Familiarity with formal verification tools and methodologies
• Knowledge of semiconductor design and verification workflows
• Exposure to Synopsys, Cadence, or Siemens EDA tool suites
• Relevant coursework, internships, or certifications in IP Design or SoC Verification