ASIC Engineering Intern, Formal Verification

Meta is seeking an ASIC Engineer Intern, Formal Verification to join our Infrastructure Silicon organization. Our servers and data centers are the foundation upon which our rapidly scaling infrastructure efficiently operates and upon which our innovative services are delivered. In this role, you will be an integral member of an ASIC team building accelerators for some of our top workloads, enabling our data centers to scale efficiently.

You will have an opportunity to apply formal verification tools and methodologies to advanced IPs and sub-systems. Working alongside experienced ASIC engineers, you will contribute to formal verification planning, assertion development, formal testbench development and proof analysis on a scoped project of your own. You will learn to translate design intent into properties, analyze counterexamples and help establish the correctness of hardware designs. Come work and learn alongside our expert ASIC engineers to build "Green" data center accelerators.
Internships are twelve (12) to sixteen (16) weeks long

Responsibilities
Develop an understanding of the architecture, microarchitecture and intended behavior of the designs under verification.
* Contribute to formal verification plans by identifying design requirements, properties to prove and scenarios to cover.
* Write SystemVerilog Assertions (SVA), assumptions and cover properties to verify design functionality, protocol behavior and corner cases.
* Develop formal testbenches and harnesses, including clock, reset and environment models, with guidance from experienced engineers.
* Run formal verification tools, analyze proof results and debug counterexamples to distinguish design bugs from property or environment issues.
* Help improve proof convergence and assess formal coverage, including checking for vacuous assertions, unreachable scenarios and overly restrictive assumptions.
* Develop scripts to automate formal runs, regressions and results analysis, and collaborate with design and verification engineers to resolve issues and confirm fixes.

Qualifications
Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
* Knowledge of computer architecture and digital logic design fundamentals, including sequential logic and finite-state machines
* Knowledge of a hardware description language such as Verilog, SystemVerilog or VHDL
* Familiarity with assertion-based verification or formal verification concepts, such as properties, assumptions and counterexamples
* Experience thinking critically and creatively about how to verify designs and solve problems
* Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
* Intent to return to a degree-program after the completion of the internship Currently has, or is in the process of obtaining, a Master's or PhD degree in Electrical Engineering, Computer Engineering or related engineering fields
* Coursework, academic projects or research involving formal methods, hardware verification or assertion-based verification
* Experience writing SystemVerilog Assertions or using formal property-checking tools such as Cadence JasperGold, Synopsys VC Formal or Siemens Questa Formal
* Experience with open-source formal verification tools and engines, such as SymbiYosys, ABC or Boolector
* Familiarity with bounded model checking, induction, safety and liveness properties, or techniques such as abstraction and assume-guarantee reasoning
* Scripting with Python, Tcl, Perl or Shell to automate verification tasks
* Experience using AI coding agents such as Claude Code or Codex to develop, debug or automate engineering workflows
* Exposure to data center application designs such as AI/ML accelerators, networking or video processing ASICs
* Familiarity with revision control systems such as Mercurial (Hg), Git or SVN