Own the design and development of Samsung's advanced custom memory controller IP.
Lead a team and exert significant influence over the entire memory controller architecture and micro-architecture.
Translate innovative concepts into cutting-edge, next-generation memory technologies.
Ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies.
Collaborate with cross-functional teams to ensure design functionality and achieve PPA goals.
Take ownership of deliverables by adhering to JEDEC standards and collaborating on SOC IP delivery.

20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD.
Proven experience in memory controller architecture and micro-architecture, leading a team through the entire development lifecycle.
Deep expertise in multiple memory technologies, such as DDR, LPDDR, PIM, GDDR, and HBM.
Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
Demonstrated success in driving architecture through RTL design for high-performance digital systems.
Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
Proficiency in scripting languages (Perl, Python) to support design and automation.
Strong communication and collaboration skills with the ability to navigate ambiguity in a fast-paced, global team environment.
Familiarity with interface protocols (AMBA, AXI, ACE, CHI) is desired.
Knowledge of AES, ECC, and RAS features is preferred.
Self-driven, curious, and passionate about logic design and innovation.

Lead Memory Controller Architect

Key skills