Develop FPGA/ASIC designs supporting design and/or verification teams
Implement FPGA/ASIC with the latest design practices and tools
Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed
Perform static timing analysis, LEC, CDC, linting, and other necessary checks
Develop Functional Coverage Models and perform Code Coverage to verify designs
Create self-checking and reusable test benches from scratch
Support FPGA-based prototyping and validation depending on program and system requirements
Validate design through hardware integration test

Bachelor of Science degree in Engineering, Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications
Experience with ASIC/FPGA design or verification
Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog
Experience with hardware-based integration and test of ASIC/FPGA designs
Master's Degree in EE, Computer Engineering/Science, or equivalent experience (Preferred)
Experience with hardware emulators, especially Palladium (Preferred)
Proficiency with hardware verification languages: System Verilog, System Verilog Assertions (Preferred)
Proficient in scripting languages: Make, Perl, Python, etc. (Preferred)
Proficient in Linux Environments (Preferred)

Associate ASIC/FPGA Design and Verification Engineer

Key skills