Key skills
Communication
About this role
Role Overview
- Ability to delve into lowest level details of CPU sub-unit design specification, implementation and its core-level impact.
- Interactions with design engineers and architects to define detailed verification scope.
- Draft detailed verification testplans.
- Define/Create a scalable constrained-random verification environment using SystemVerilog and UVM.
- Drive stimulus, comprehensive coverage strategy to show continuous progress towards tape-out.
- Lookout for continuous improvement of verification flows/processes.
- Ability to lead and provide detailed technical guidance to junior verification engineers.
- Agility to work on multiple tasks/projects.
Requirements
- BS/MS (or equivalent experience) with 5+ years of experience.
- Experience with FrontEnd CPU verification (e.g. Branch Prediction, Instruction Cache, TLB)
- Background with UVM verification methodology.
- Experience or knowledge with SystemVerilog, SVA or functional coverage.
- Good communication skills and ability & desire to work as a team player.
- Experience with ARM A64, X86 Architectures.
Benefits
- equity
- benefits