About this role

Lead and drive architectural specification and design activities for Coherency Manager and Cache Controller IP to closure.
Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications.
Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell.
Mentor design engineers, providing technical guidance and leadership within the verification team.

Master’s degree or higher in Electronics/Electrical/Computer Engineering.
15+ years of relevant verification experience, specifically in CPU or complex SoC verification.
Proven expertise in Multicore and Multicluster Coherency, Cache Controllers, or similar blocks.
Proficiency in SystemVerilog, Verilog, C/C++, and Assembly.
Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI.
Strong scripting skills in Python, Perl, TCL, or Shell.
Experience with CPU architectures, particularly RISC-V, ARM, or MIPS.

Opportunity to be part of a dynamic team creating industry-leading RISC-V processors.
Autonomy with extensive support from industry experts.
Opportunities for significant career growth and technical advancement.
Competitive compensation and comprehensive benefits package.

DMTS NOC Cache Coherency Architect

Key skills