Develop logic design, register transfer level (RTL) coding, and implement DFT architectures including SCAN, MBIST, BSCAN, and TAP.
Collaborate in the definition of architecture and microarchitecture features for DFT blocks and subsystems.
Optimize logic to achieve power, performance, area, timing, test coverage, and defect per million (DPM) goals.
Write and generate RTL and structural code for DFT integration, ensuring design integrity for physical implementation.
Review and execute verification plans to ensure design features meet architecture specifications.
Resolve RTL test failures and implement corrective measures to ensure feature correctness.
Support SoC customers for successful integration of DFT blocks, contributing to high-quality IP and SoC designs.
Develop high-volume manufacturing (HVM) test content for rapid bring-up and production deployment on automatic test equipment (ATE).
Collaborate with post-silicon and manufacturing teams to verify features in silicon and support debugging requirements.

DFT Design Engineer

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