Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die
Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic)
Collaborate with SoC architects to translate architectural and micro-architectural specifications into high-quality RTL implementations
Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure
Support design verification through debug of simulation, emulation, and formal results; resolve functional, performance, and connectivity issues
Work closely with physical design teams to address synthesis, timing, power, and floor planning considerations
Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues
Contribute to design documentation, block specifications, and design reviews
Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds
Continuously improve build quality, reusability, and development efficiency through established guidelines and automation
Requirements
Strong experience in digital SoC design and RTL development
Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies
Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and design sign-off considerations
Working knowledge of design verification concepts and debug workflows
Experience integrating complex IP blocks into large SoCs
Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens
Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting)
Ability to work effectively in a global, multi-functional engineering environment
Strong analytical and problem-solving skills with attention to detail
Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field