Designs, implements, and verifies the layout design of test structures and circuits
Develops custom layout design of analog blocks, complex digital, mixed signal blocks, standard cell libraries, or memory compilers
Performs detailed physical array planning, area optimization, digital block synthesis, critical wire analysis, custom leaf, cell layout, and compiler assembly coding
Conducts complete layout verification including design rule compliance, SoC integration specs, electron migration, voltage drop (IR), selfheat, ESD, and other reliability checks
Uses custom auto-routers and custom placers to efficiently construct layout
Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests
Develops and drives new and innovative layout methods to improve productivity and quality
Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology issues used for layout design.

Bachelor’s Degree in Electrical/Computer Engineering or related field and 6+ years of experience OR a Master's degree in Electrical/Computer Engineering or related field and 4+ years of experience OR a PhD in Electrical/Computer Engineering or related field and 2+ years of experience
AMS/CMOS VLSI design concepts, flows, and EDA tools
Layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS)
Programming/scripting in C/C++, Python
UNIX/Linux operating systems
8+ years of experience in layout design, Cadence Virtuoso Layout Suite, layout debug (DRC, LVS)
4+ years of experience in EDA Tools, Flows, and Methodology (TFM) development
1+ year of experience with Cadence SKILL programming languages
Experience leading and coordinating small/medium size group of layout designers
Strong initiative, analytical/problem solving skills, communication skills, team working skills, ability to multitask and be able to work with a diverse team located in different geos.

Senior Layout Design Engineer

Key skills