Principal SoC Design Verification Engineer, HBM

Role Overview

• Develop and complete verification plans for SoC-level and subsystem builds
• Develop verification components including UVM agents, scoreboards, checkers, assertions, and coverage models
• Drive functional coverage closure
• Verify complex IP integrations
• Collaborate with RTL designers to debug functional issues
• Participate in SoC-level integration verification
• Leverage hardware emulation/acceleration platforms
• Support post-silicon validation and debugging

Requirements

• Minimum 10 years of experience
• Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field
• Strong experience in SoC or IP-level design verification
• Proficiency in SystemVerilog and UVM
• Solid understanding of SoC architectures
• Experience debugging complex functional issues across RTL, testbench, and system-level interactions
• Familiarity with industry EDA tools (Cadence, Synopsys, and/or Siemens)
• Experience with scripting or automation using Python, Perl, TCL, or shell

Tech Stack

• Perl
• Python

Benefits

• Choice of medical, dental and vision plans
• Income protection programs
• Paid family leave
• Robust paid time-off program
• Paid holidays