Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements.
Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment.
Finds and implements corrective measures to resolve failing tests.
Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.

BS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 8+ years of relevant industry experience in Design verification, System Verilog and OVM/UVM or
MS degree in Computer Engineering/Computer Science/Electrical Engineering or related field with 6 + years of relevant industry experience or
PhD in Computer Engineering/Computer Science/Electrical Engineering or related field with & 4+ years in the following: Design verification System Verilog OVM/UVM
experience in validation flow right from test plan creation to verification closure
waveform debug
functional coverage
code coverage
VCS NLP and non-NLP simulations
GLS
knowledge of DDRPHY validation with good hold on DFI/DDR/LPDDR protocols
experience in scripting skills in Python/Perl
exposure to Formal Property Verification and Git/Perforce/CVS version control

Senior Design Verification Engineer – Mixed Signal IP

Key skills