About this role

Responsible for the micro-architecture and design of the AI Compute sub-system modules including Hardware Execution Engines.
Own design, document, execute and deliver fully verified, high performance, area, and power efficient RTL.
Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies.
Design and implement logic functions that enable efficient test and debug.
Participate in silicon bring-up and validation for blocks owned.

Master’s degree in electrical engineering, Computer Engineering or Computer Science with 12 + years of meaningful work experience
Experience in micro-architecture and RTL development (Verilog/System Verilog)
Exposure to Computer Architecture & Arithmetic is required
Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis
Strong interpersonal skills and an excellent teammate

Principal Digital Design Engineer, Micro-Architect

Key skills