About this role

Interfacing with architecture, design, physical implementation and software teams.
Reading and analyzing system requirements and architecture requirement documents.
Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++.
Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
Using standard tools and flows of the verification process.
Create and execute test cases to verify functionality, performance, and robustness in embedded C and SV.
Identify, isolate, and debug issues found during verification.

Master Degree in relevant field.
Min 7 years of experience in relevant field of Verification of complex SoC or IP.
Experience in SystemVerilog/UVM and SystemC/C++
Experience in Constrained random, Functional Coverage development, design debug.
Experience in Formal Verification, UPF.
Experience in HW-SW co-verification and simulation.
Some previous experience in Firmware based verification is a good to have.
Some knowledge of scripting languages like Bash/Perl/Python.
Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
Good level of English, both written and spoken is mandatory.

Senior Engineer, Functional Verification

Key skills