Interfacing with architecture, design, physical implementation and software teams.
Reading and analysing the system requirements and architecture requirement documents.
Developing detailed Test and Coverage plans based on the Architecture and Micro-architecture.
Developing Verification Methodology to ensure scalability and portability across environments.
Executing Verification Plans, including Design Bring-up, DV environment Bring-up, regressions and debug of the test failures.
Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.
Identify, isolate, and debug issues found during verification.
Work closely with cross-functional teams to achieve verification closure.
Mentoring and training the next generation of verification engineers.
Coordinating functional verification teams.

Master Degree in relevant field.
Min 15 years of experience in relevant field of Verification of complex SoC or IP.
Experience in SystemVerilog/UVM.
Experience in SystemC/C++.
Experience in Constrained random, Functional Coverage development, design debug.
Experience in Formal Verification, UPF.
Experience in HW-SW co-verification and simulation.
Some previous experience in Firmware based verification is a good to have.
Some knowledge of scripting languages like Bash/Perl/Python.
Use of verification management tools.
Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
Good level of English, both written and spoken is mandatory.

Principal Functional Verification Engineer

Key skills