Interfacing with architecture, design, physical implementation and software teams.
High-level modelling, UVM, HW/SW Co-Debug, Simulation Acceleration support.
Reading and analysing the system requirements and architecture requirement documents.
Developing Verification environment development and maintenance in SystemVerilog/UVM/SystemC/C++, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions and Debug of the test failures.
Using standard tools and flows of the verification process (Simulators, Coverage Analyzers, Unix, Continuous Integration, Bug Tracking, …).
Create and execute testcases to verify the functionality, performance, and robustness in embedded C and SV.
Identify, isolate, and debug issues found during verification, leveraging simulation and debugging tools to root-cause failures and drive resolution with design and architecture teams.
Work closely with cross-functional teams to achieve verification closure, conducting coverage analysis, bug tracking, and regression testing to ensure the quality and completeness of verification activities.
Participation to verification methodology improvements.
Organize work and deliverables between skills, internal and external teams.
Opportunities for mentoring and training the next generation of verification engineers.

Master Degree in relevant field.
Min 7 years of experience in relevant field of Verification of complex SoC or IP.
Experience in SystemVerilog/UVM/SystemC/C++.
Experience in Constrained random, Functional Coverage development, design debug.
Experience in Formal Verification, UPF.
Experience in HW-SW co-verification and simulation.
Some previous experience in Firmware based verification is a good to have.
Some knowledge of scripting languages like Bash/Perl/Python.
Use of verification management tools.
Strong debugging and problem-solving skills, with the ability to effectively analyze and resolve complex verification issues.
Good level of English, both written and spoken is mandatory.

Senior Engineer – Functional Verification

Key skills