Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits
Perform circuit modeling, sensitivity analyses, and assist in developing validation through widely recognized simulation software and tools
Design on-silicon test chips and lead required tape-out revisions
Coordinate and collaborate with the layout team, including floor-planning, placement, and routing
Carry out verification procedures with modeling and simulation using industry-standard simulators

8+ years of demonstrated ability in communicating with technical and non-technical team members across a large organization
Demonstrated experience in mix-signal, digital, or analog IC design and development for volatile or nonvolatile memory technology
Proven experience in IC design with exposure to Regulator, Charge Pump, Oscillator, Current reference, Bandgap, and Comparator design experience
Experience with modeling and simulation of ICs using SPICE and Verilog
BSEE or MSEE in Electrical Engineering with a minimum of 8 years of relevant Semiconductor Manufacturing experience.
MSEE + 8 years’ post-graduate mix-signal or analog IC design experience is preferred.
8+ years of exposure to circuit debugging in collaboration with other engineering teams
Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extraction)

Principal Design Engineer, Pathfinding

Key skills