Formal Verification Engineer, Co-Op

Role Overview

• Support the formal verification team to follow, and improve, defined methodology practices.
• Develop test plans and verification methodologies to formally verify the microarchitecture and design.
• Perform failure analysis and resolution, coverage analysis, and population.
• Implement and improve functional and formal verification.

Requirements

• Master’s or PhD degree in Electrical or Computer Engineering
• Knowledge in designing and implementing verification environments for module-level designs.
• Proficiency in System Verilog.
• Familiarity with scripting languages such as Python, Perl, TCL, Bash.
• Experienced or knowledge in UVM or equivalent methodologies.
• Knowledge in formal property languages such as SVA.
• Knowledge in property-based model-checking.
• Knowledgeable in signal processing, analog or digital design fundamentals.

Tech Stack

• Perl
• Python

Benefits

• Interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference.
• Meaningful community engagement and delivering enjoyable employee experiences at every turn.