Drive best-in-class product maturity which includes bits per wafers (yield), product grades (Repair Density and DPM) at the fastest speed and cycle of learning
Collaborate with YE, Device, RDA, Metrology team to resolve top yield issues, develop inline visibility to enable fast yield ramp and minimize excursion
Identify best known method and business process from DRAM/NAND sites and drive for alignment and standardize across network
Requirements
In depth knowledge of processes across different loops or functions (FEOL, MOL, CELL, BEOL) to identify best optimum process integration solution
Knowledge on product and circuit design will be plus
Travel to Micron sites as necessary for face to face collaboration