About this role

Performs functional logic verification of an integrated SoC to ensure design will meet specifications
Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment
Executes verification plans and defines and runs emulation and system simulation models to verify the design
Replicates, root causes, and debugs issues in the presilicon environment
Finds and implements corrective measures to resolve failing tests
Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams
Incorporates and executes security activities within test plans, including regression and debug tests

graduate with a Bachelors or Masters Degree in Electrical Engineering and/or Computer Engineering and/or Computer Science
1+ years SystemVerilog and UVM experience
2+ years Python for test automation
6+ months C/C++ and scripting proficiency (Perl, Tcl, Shell)
1+ years pre-silicon verification experience
6+ months Linux/Unix and version control (Git, Perforce)
6+ months Regression testing and CI/CD pipelines
6+ months Security verification methodologies

SOC Design Verification Engineer

Key skills